Intel's cornered GF CTO: "three minutes of the world" wafer war begins

By Intel 104

Intel's cornered GF CTO: "three minutes of the world" wafer war begins

A few days ago, Intel's manufacturing process route was disclosed. Although ASML added 7nm, 5nm, 3nm, 2nm, and 1.4nm to the roadmap without authorization, Moore's Law, which is once every two years, is still in progress.

The latest news shows that Intel has recently recruited Dr. Gary Patton, former CTO of GlobalFoundries and former director of IBM microelectronics business. Of course, in order to do a good job of the new CPU / GPU architecture, Intel has also dug out a large number of industry bulls such as Raja Koduri and Jim Keller.

At present, GF has changed its investment strategy, cancelled 7nm and 5nm process research and development, and focused on 14 / 12nm process and special 22FDX, 12FDX. So it's a good thing that Gary Patton can still make front-line research and development.

At present, the battle in the fab has become a "three minutes of the world" pattern, these three are Intel, TSMC, Samsung.

In terms of Intel, the two-year-new update process reported in the previous report said that although this is an oolong incident, this is the first 1.4nm process that was reported by ASML. Of course, Intel also emphasized that between each process node, there will be iterative + and ++ versions in order to extract performance from each process node. But in terms of EUV, it still needs to be installed in EUV equipment until 2021.

In terms of TSMC, it is well known that it is a "proficient" player in the EUV process. It is true that wafer fabs often use some techniques in the marking process to cause TSMC 7nm process to have the same performance as Intel 10nm process. But purely from the number point of view, at present TSMC has entered the countdown of mass production in 5nm, 3nm and 2nm have been on the agenda and far earlier than Intel. But with previous experience, perhaps there will still be no difference in performance.

Samsung, on the other hand, is planning steadily, from the four main nodes of 14nm, 10nm, 7nm, and 3nm. After the 3nm node, Samsung has to abandon FinFET and switch to GAA transistors. The optimization and improvement of the 3GAE process and 3GAP process is still far away.

The two-year update of Moore's Law is still ongoing, and if it is below the 1nm process, how to continue Moore's Law will become a serious problem.

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