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SN74LVC841ADWRG4

SN74LVC841ADWRG4
Mfr. #:
SN74LVC841ADWRG4
Beschreibung:
Latches 10B Bus Interface DType Latch
Lebenszyklus:
Neu von diesem Hersteller.
Datenblatt:
SN74LVC841ADWRG4 Datenblatt
Die Zustellung:
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ECAD Model:
Mehr Informationen:
SN74LVC841ADWRG4 Mehr Informationen SN74LVC841ADWRG4 Product Details
Produkteigenschaft
Attributwert
Hersteller:
Texas Instruments
Produktkategorie:
Verschlüsse
RoHS:
Y
Anzahl Kreise:
1 Circuit
Logiktyp:
D-Typ-Verriegelung
Logikfamilie:
LVC
Polarität:
Nicht invertiert
Ruhestrom:
10 uA
Anzahl der Ausgangsleitungen:
10 Line
Ausgangsstrom auf hohem Niveau:
- 24 mA
Niedriger Ausgangsstrom:
32 mA
Ausbreitungsverzögerungszeit:
7.5 ns at 2.7 V, 6.7 ns at 3.3 V
Versorgungsspannung - Max.:
3.6 V
Versorgungsspannung - Min.:
1.65 V
Minimale Betriebstemperatur:
- 40 C
Maximale Betriebstemperatur:
+ 85 C
Paket / Koffer:
SOIC-24
Verpackung:
Spule
Funktion:
Transparent
Höhe:
2.35 mm
Länge:
15.4 mm
Ausgabetyp:
3-State
Typ:
D-Typ
Breite:
7.52 mm
Marke:
Texas Instruments
Montageart:
SMD/SMT
Anzahl der Kanäle:
10 Channel
Anzahl der Eingabezeilen:
10 Line
Betriebsversorgungsspannung:
1.8 V, 2.5 V, 3.3 V
Produktart:
Verschlüsse
Reset-Typ:
Kein Zurücksetzen
Werkspackungsmenge:
1
Unterkategorie:
Logik-ICs
Gewichtseinheit:
0.021006 oz
Tags
SN74LVC841ADWR, SN74LVC841ADW, SN74LVC841AD, SN74LVC841A, SN74LVC84, SN74LVC8, SN74LVC, SN74LV, SN74L, SN74, SN7
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
*** Stop Electro
Bus Driver, LVC/LCX/Z Series, 1-Func, 10-Bit, True Output, CMOS, PDSO24
***i-Key
IC D-TYPE LATCH SGL 3-ST 24SOIC
***as Instruments
This 10-bit bus-interface D-type latch is designed for 1.65-V to 3.6-V VCC operation. The SN74LVC841A is designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The ten latches are transparent D-type latches. The device has noninverting data (D) inputs and provides true data at its outputs. A buffered output-enable (OE)\ input can be used to place the ten outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE\ does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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Verfügbarkeit
Aktie:
Available
Auf Bestellung:
1500
Menge eingeben:
Der aktuelle Preis von SN74LVC841ADWRG4 dient nur als Referenz. Wenn Sie den besten Preis erhalten möchten, senden Sie bitte eine Anfrage oder senden Sie eine direkte E-Mail an unser Verkaufsteam [email protected]
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