SN74ACT7805-20DLR

SN74ACT7805-20DLR
Mfr. #:
SN74ACT7805-20DLR
Beschreibung:
FIFO 256 x 18 synchronous FIFO memory
Lebenszyklus:
Neu von diesem Hersteller.
Datenblatt:
SN74ACT7805-20DLR Datenblatt
Die Zustellung:
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ECAD Model:
Mehr Informationen:
SN74ACT7805-20DLR Mehr Informationen SN74ACT7805-20DLR Product Details
Produkteigenschaft
Attributwert
Hersteller:
Texas Instruments
Produktkategorie:
FIFO
RoHS:
Y
Paket / Koffer:
SSOP-56
Verpackung:
Spule
Marke:
Texas Instruments
Montageart:
SMD/SMT
Betriebsversorgungsspannung:
4.5 V to 5.5 V
Produktart:
FIFO
Werkspackungsmenge:
1
Unterkategorie:
Speicher & Datenspeicherung
Gewichtseinheit:
0.024508 oz
Tags
SN74ACT7805-2, SN74ACT7805, SN74ACT780, SN74ACT78, SN74ACT7, SN74ACT, SN74AC, SN74A, SN74, SN7
Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***et
FIFO Mem Sync Dual Width Uni-Dir 256 x 18 56-Pin SSOP T/R
***i-Key
IC CLOCKED FIFO 256X18 56-SSOP
***as Instruments
The SN74ACT7805 is a 256-word 18-bit clocked FIFO suited for buffering asynchronous data paths up to 67-MHz clock rates and 12-ns access times. Two devices can be configured for bidirectional data buffering without additional logic. Multiple distributed VCC and GND pins, along with Texas Instruments patented output edge control (OECTM) circuit, dampen simultaneous switching noise. The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2\ is low, and IR is high. Data is read from memory on the rising edge of RDCLK when RDEN\, OE1\, and OE2\ are low and OR is high. The first word written to memory is clocked through to the output buffer, regardless of the RDEN\, OE1\, and OE2\ levels. The OR flag indicates that valid data is present on the output buffer. The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET\ must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the input-ready (IR), output-ready (OR), and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up. The SN74ACT7805 is characterized for operation from 0C to 70C.
Teil # Beschreibung Aktie Preis
SN74ACT7805-20DLR
DISTI # SN74ACT7805-20DLR-ND
IC CLOCKED FIFO 256X18 56-SSOP
RoHS: Compliant
Min Qty: 1000
Container: Tape & Reel (TR)
Limited Supply - Call
    SN74ACT7805-20DLR
    DISTI # 595-SN74ACT780520DLR
    FIFO 256 x 18 synchronous FIFO memory
    RoHS: Compliant
    0
      SN74ACT7805-20DLRFIFO, 256X18, 13ns, Synchronous, CMOS, PDSO56
      RoHS: Compliant
      36750
      • 1000:$15.7100
      • 500:$16.5400
      • 100:$17.2200
      • 25:$17.9600
      • 1:$19.3400
      Bild Teil # Beschreibung
      SN74ACT7805-20DLR

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      Verfügbarkeit
      Aktie:
      Available
      Auf Bestellung:
      4000
      Menge eingeben:
      Der aktuelle Preis von SN74ACT7805-20DLR dient nur als Referenz. Wenn Sie den besten Preis erhalten möchten, senden Sie bitte eine Anfrage oder senden Sie eine direkte E-Mail an unser Verkaufsteam [email protected]
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