74ALVCH16835DLG4

74ALVCH16835DLG4
Mfr. #:
74ALVCH16835DLG4
Beschreibung:
IC UNIV BUS DVR 18BIT 56SSOP
Lebenszyklus:
Neu von diesem Hersteller.
Datenblatt:
74ALVCH16835DLG4 Datenblatt
Die Zustellung:
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Mehr Informationen:
74ALVCH16835DLG4 Mehr Informationen 74ALVCH16835DLG4 Product Details
Produkteigenschaft
Attributwert
Hersteller
Texas Instruments
Produktkategorie
Logik - Universelle Busfunktionen
Serie
74ALVCH
Verpackung
Rohr
Paket-Koffer
56-BSSOP (0.295", 7.50mm Width)
Betriebstemperatur
-40°C ~ 85°C
Befestigungsart
Oberflächenmontage
Spannungsversorgung
1.65 V ~ 3.6 V
Lieferanten-Geräte-Paket
56-SSOP
Anzahl der Schaltungen
18-Bit
Anzahl der Eingänge
-
Strom-Ausgang-High-Low
24mA, 24mA
Logik-Typ
Universeller Busfahrer
Tags
74ALVCH16835, 74ALVCH1683, 74ALVCH168, 74ALVCH1, 74ALVCH, 74ALVC, 74ALV, 74AL, 74A
Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
Our experienced sales team and tech support team back our services to satisfy all our customers.

we buy and manage excess electronic components, including excess inventory identified for disposal.
Email us if you have excess stock to sell.

Email: [email protected]

Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***i-Key
IC UNIV BUS DVR 18BIT 56SSOP
***eco
18-BIT DFF MEMORY BUFFER
***as Instruments
This 18-bit universal bus driver is designed for 1.65-V to 3.6-V VCC operation. Data flow from A to Y is controlled by the output-enable (OE)\ input. The device operates in the transparent mode when the latch-enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
Teil # Beschreibung Aktie Preis
74ALVCH16835DLG4
DISTI # 74ALVCH16835DLG4-ND
IC UNIV BUS DVR 18BIT 56SSOP
RoHS: Compliant
Min Qty: 420
Container: Tube
Limited Supply - Call
    74ALVCH16835DLG4
    DISTI # 595-74ALVCH16835DLG4
    Universal Bus Functions 18B Universal Bus Dr
    RoHS: Compliant
    0
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      Verfügbarkeit
      Aktie:
      Available
      Auf Bestellung:
      3500
      Menge eingeben:
      Der aktuelle Preis von 74ALVCH16835DLG4 dient nur als Referenz. Wenn Sie den besten Preis erhalten möchten, senden Sie bitte eine Anfrage oder senden Sie eine direkte E-Mail an unser Verkaufsteam [email protected]
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      Aufgrund von Halbleiterknappheit ab 2021 ist der untere Preis der Normalpreis vor 2021. Bitte senden Sie eine Anfrage zur Bestätigung.
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