SN74ALVC7813-25DLR

SN74ALVC7813-25DLR
Mfr. #:
SN74ALVC7813-25DLR
Beschreibung:
FIFO 64 X 18 CLOCKED FIFO
Lebenszyklus:
Neu von diesem Hersteller.
Datenblatt:
SN74ALVC7813-25DLR Datenblatt
Die Zustellung:
DHL FedEx Ups TNT EMS
Zahlung:
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ECAD Model:
Mehr Informationen:
SN74ALVC7813-25DLR Mehr Informationen SN74ALVC7813-25DLR Product Details
Produkteigenschaft
Attributwert
Hersteller:
Texas Instruments
Produktkategorie:
FIFO
Datenbusbreite:
18 bit
Busrichtung:
Unidirektional
Speichergröße:
1.125 kbit
Timing-Typ:
Synchron
Organisation:
64 k x 18
Anzahl Kreise:
2
Maximale Taktfrequenz:
40 MHz
Zugriffszeit:
15 ns
Versorgungsspannung - Max.:
3.6 V
Versorgungsspannung - Min.:
3 V
Versorgungsstrom - Max.:
0.04 mA
Minimale Betriebstemperatur:
0 C
Maximale Betriebstemperatur:
+ 70 C
Paket / Koffer:
SSOP-56
Höhe:
2.59 mm
Breite:
7.49 mm
Marke:
Texas Instruments
Montageart:
SMD/SMT
Betriebsversorgungsspannung:
3 V to 3.6 V
Produktart:
FIFO
Unterkategorie:
Speicher & Datenspeicherung
Gewichtseinheit:
0.024508 oz
Tags
SN74ALVC7813-2, SN74ALVC7813, SN74ALVC781, SN74ALVC7, SN74ALVC, SN74ALV, SN74AL, SN74A, SN74, SN7
Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***et
FIFO Mem Sync Dual Width Uni-Dir 64 x 18 56-Pin SSOP T/R
***i-Key
IC MEMORY FIFO 64X18 56-SSOP
***as Instruments
The SN74ALVC7813 is suited for buffering asynchronous data paths up to 50-MHz clock rates and 13-ns access times. This device is designed for 3-V to 3.6-V VCC operation. Two devices can be configured for bidirectional data buffering without additional logic. The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2\ is low, and input ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN\, OE1\, and OE2\ are low and output ready (OR) is high. The first word written to memory is clocked through to the output buffer, regardless of the RDEN\, OE1\, and OE2\ levels. The OR flag indicates that valid data is present on the output buffer. The FIFO can be reset asynchronously to WRTCLK and RDCLK. Reset (RESET\) must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up. The SN74ALVC7813 is characterized for operation from 0C to 70C.
Teil # Beschreibung Aktie Preis
SN74ALVC7813-25DLR
DISTI # SN74ALVC7813-25DLR-ND
IC MEMORY FIFO 64X18 56-SSOP
RoHS: Compliant
Min Qty: 1000
Container: Tape & Reel (TR)
Limited Supply - Call
    SN74ALVC7813-25DLRFIFO, 64X18, 15ns, Synchronous, CMOS, PDSO56
    RoHS: Compliant
    9000
    • 1000:$3.1800
    • 500:$3.3500
    • 100:$3.4900
    • 25:$3.6400
    • 1:$3.9200
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    OMO.#: OMO-SN74ALVC7814-25DL-TEXAS-INSTRUMENTS

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    Mfr.#: SN74ALVC7804-25DL

    OMO.#: OMO-SN74ALVC7804-25DL-TEXAS-INSTRUMENTS

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    Verfügbarkeit
    Aktie:
    Available
    Auf Bestellung:
    1500
    Menge eingeben:
    Der aktuelle Preis von SN74ALVC7813-25DLR dient nur als Referenz. Wenn Sie den besten Preis erhalten möchten, senden Sie bitte eine Anfrage oder senden Sie eine direkte E-Mail an unser Verkaufsteam [email protected]
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