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SN74V3690-6PEU

SN74V3690-6PEU
Mfr. #:
SN74V3690-6PEU
Beschreibung:
FIFO 32768 x 36 Synch FIFO Memory
Lebenszyklus:
Neu von diesem Hersteller.
Datenblatt:
SN74V3690-6PEU Datenblatt
Die Zustellung:
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ECAD Model:
Mehr Informationen:
SN74V3690-6PEU Mehr Informationen SN74V3690-6PEU Product Details
Produkteigenschaft
Attributwert
Hersteller:
Texas Instruments
Produktkategorie:
FIFO
RoHS:
N
Datenbusbreite:
36 bit
Busrichtung:
Unidirektional
Speichergröße:
1.125 Mbit
Timing-Typ:
Synchron
Organisation:
32 k x 36
Anzahl Kreise:
2
Maximale Taktfrequenz:
166 MHz
Zugriffszeit:
4.5 ns
Versorgungsspannung - Max.:
3.45 V
Versorgungsspannung - Min.:
3.15 V
Versorgungsstrom - Max.:
40 mA
Minimale Betriebstemperatur:
0 C
Maximale Betriebstemperatur:
+ 70 C
Paket / Koffer:
LQFP-128
Verpackung:
Tablett
Höhe:
1.4 mm
Serie:
SN74V3690
Breite:
14 mm
Marke:
Texas Instruments
Montageart:
SMD/SMT
Feuchtigkeitsempfindlich:
ja
Betriebsversorgungsspannung:
3.3 V
Produktart:
FIFO
Werkspackungsmenge:
72
Unterkategorie:
Speicher & Datenspeicherung
Gewichtseinheit:
0.021693 oz
Tags
SN74V369, SN74V3, SN74V, SN74, SN7
Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
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we buy and manage excess electronic components, including excess inventory identified for disposal.
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Email: [email protected]

Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
    M***a
    M***a
    RU

    The parcel was received, came on time. i recommend.

    2019-05-17
    E**a
    E**a
    US

    The goods did not come. Money returned

    2019-04-20
***as Instruments
32768 x 36 Synchronous FIFO Memory 128-LQFP 0 to 70
***ical
FIFO Mem Sync Dual Depth/Width Uni-Dir 32K x 36 128-Pin LQFP Tray
*** Stop Electro
FIFO, 32KX36, 4.5ns, Synchronous, CMOS, PQFP128
***ark
32768 X 36 SYNCHRONOUS FIFO MEMORY, LQFP128
***i-Key
IC 32768X36 FIFO MEMORY 128LQFP
***DA Technology Co., Ltd.
Product Description Demo for Development.
***as Instruments
1024 x 36 Synchronous FIFO Memory 128-LQFP 0 to 70
***et
FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 36 128-Pin LQFP Tray
***ark
FIFO Logic IC; Frequency Max:166MHz; Supply Voltage Min:3.15V; Supply Voltage Max:3.45V; Package/Case:128-LQFP; No. of Pins:128; Operating Temperature Range:0°C to +70°C; Leaded Process Compatible:No ;RoHS Compliant: No
***as Instruments
4096 x 36 Synchronous FIFO Memory 128-LQFP 0 to 70
***ical
FIFO Mem Sync Dual Depth/Width Uni-Dir 4K x 36 128-Pin LQFP Tray
***ark
FIFO Logic IC; Frequency Max:166MHz; Supply Voltage Min:3.15V; Supply Voltage Max:3.45V; Package/Case:128-LQFP; No. of Pins:128; Operating Temperature Range:0°C to +70°C; Leaded Process Compatible:No ;RoHS Compliant: No
***as Instruments
4096 x 36 Synchronous FIFO Memory 128-LQFP 0 to 70
***ical
FIFO Mem Sync Dual Depth/Width Uni-Dir 4K x 36 128-Pin LQFP Tray
***ark
FIFO Logic IC; Frequency Max:166MHz; Supply Voltage Min:3.15V; Supply Voltage Max:3.45V; Package/Case:128-LQFP; No. of Pins:128; Operating Temperature Range:0°C to +70°C; Leaded Process Compatible:No ;RoHS Compliant: No
***INS
The SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, and SN74V3690 are exceptionally deep, high-speed CMOS, first-in first-out (FIFO) memories, with clocked read and write controls and a flexible bus-matching ×36/×18/×9 data flow. These FIFOs offer several key user benefits:
***ASIN
Bus-matching synchronous FIFOs are particularly appropriate for network, video, signal processing, telecommunications, data communications, and other applications that need to buffer large amounts of data and match buses of unequal sizes.
***as Instruments Inc.
Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume 36-bit, 18-bit, or 9-bit width, as determined by the state of external control pins’ input width (IW), output width (OW), and bus matching (BM) during the master-reset cycle.
***AS USD
The input port is controlled by write-clock (WCLK) and write-enable (WEN\) inputs. Data is written into the FIFO on every rising edge of WCLK when WEN\ is asserted. The output port is controlled by read-clock (RCLK) and read-enable (REN\) inputs. Data is read from the FIFO on every rising edge of RCLK when REN\ is asserted. An output-enable (OE\) input is provided for 3-state control of the outputs.
***AS INSTRUMENTS INC
The frequencies of the RCLK and WCLK signals can vary from 0 to fMAX, with complete independence. There are no restrictions on the frequency of one clock input with respect to the other.
***XS
There are two possible timing modes of operation with these devices: first-word fall-through (FWFT) mode and standard mode.
***NS
In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. REN\ need not be asserted for accessing the first word. However, subsequent words written to the FIFO do require a low on REN\ for access. The state of the FWFT/SI input during master reset determines the timing mode.
***AS INSRUMENT
For applications requiring more data-storage capacity than a single FIFO can provide, the FWFT timing mode permits depth expansion by chaining FIFOs in series (i.e., the data outputs of one FIFO are connected to the corresponding data inputs of the next). No external logic is required.
***
In standard mode, the first word written to an empty FIFO does not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating REN\ and enabling a rising RCLK edge, shifts the word from internal memory to the data output lines.
***XS
These FIFOs have five flag pins: empty flag or output ready (EF\/OR\), full flag or input ready (FF\/IR\), half-full flag (HF), programmable almost-empty flag (PAE\), and programmable almost-full flag (PAF\). The EF\ and FF\ functions are selected in standard mode. The IR\ and OR\ functions are selected in FWFT mode. HF\, PAE\, and PAF\ are always available for use, regardless of timing mode.
***ASI
PAE\ and PAF\ can be programmed independently to switch at any point in memory. Programmable offsets determine the flag-switching threshold and can be loaded by parallel or serial methods. Eight default offset settings are also provided, so that PAE\ can be set to switch at a predefined number of locations from the empty boundary. The PAF\ threshold also can be set at similar predefined values from the full boundary. The default offset values are set during master reset by the state of the FSEL0, FSEL1, and LD\.
***AS INS
For serial programming, SEN\, together with LD\, loads the offset registers via the serial input (SI) on each rising edge of WCLK. For parallel programming, WEN\, together with LD\, loads the offset registers via Dn on each rising edge of WCLK. REN\, together with LD\, can read the offsets in parallel from Qn on each rising edge of RCLK, regardless of whether serial parallel offset loading has been selected.
***as Instr.
During master reset (MRS\), the read and write pointers are set to the first location of the FIFO. The FWFT pin selects standard mode or FWFT mode.
***AS INSRUMENTS
Partial reset (PRS\) also sets the read and write pointers to the first location of the memory. However, the timing mode, programmable-flag programming method, and default or programmed offset settings existing before partial reset remain unchanged. The flags are updated according to the timing mode and offsets in effect. PRS\ is useful for resetting a device in mid-operation, when reprogramming programmable flags would be undesirable.
***TEXAS
Also, the timing modes of PAE\ and PAF\ outputs can be selected. Timing modes can be set to be either asynchronous or synchronous for PAE\ and PAF\.
***OMO Electronic
If the asynchronous PAE\/PAF\ configuration is selected, PAE\ is asserted low on the low-to-high transition of RCLK. PAE\ is reset to high on the low-to-high transition of WCLK. Similarly, PAF\ is asserted low on the low-to-high transition of WCLK, and PAF\ is reset to high on the low-to-high transition of RCLK.
***OMO Electronic
If the synchronous PAE\/PAF\ configuration is selected , the PAE\ is asserted and updated on the rising edge of RCLK only, and not WCLK. Similarly, PAF\ is asserted and updated on the rising edge of WCLK only, and not RCLK. The mode desired is configured during master reset by the state of the programmable flag mode (PFM).
***ASIN
The retransmit function allows data to be reread from the FIFO more than once. A low on the retransmit (RT\) input during a rising RCLK edge initiates a retransmit operation by setting the read pointer to the first location of the memory array. Zero-latency retransmit timing mode can be selected using the retransmit timing mode (RM). During master reset, a low on RM selects zero-latency retransmit. A high on RM during master reset selects normal latency.
***
If zero-latency retransmit operation is selected, the first data word to be retransmitted is placed on the output register, with respect to the same RCLK edge that initiated the retransmit, if RT\ is low.
***AS INSTR
See Figures 11 and 12 for normal latency retransmit timing. See Figures 13 and 14 for zero-latency retransmit timing.
***as Instr.
The devices can be configured with different input and output bus widths (see Table 1).
***ASIN
A big-endian/little-endian data word format is provided. This function is useful when data is written into the FIFO in long-word (×36/×18) format and read out of the FIFO in small-word (×18/×9) format. If big-endian mode is selected, the most significant byte (MSB) (word) of the long word written into the FIFO is read out of the FIFO first, followed by the least-significant byte (LSB). If little-endian format is selected, the LSB of the long word written into the FIFO is read out first, followed by the MSB. The mode desired is configured during master reset by the state of the big-endian/little-endian (BE\) pin (see Figure 4 for the bus-matching byte arrangement).
***NS
The interspersed/noninterspersed parity (IP) bit function allows the user to select the parity bit in the word loaded into the parallel port (D0-Dn) when programming the flag offsets. If interspersed-parity mode is selected, the FIFO assumes that the parity bit is located in bit positions D8, D17, D26, and D35 during the parallel programming of the flag offsets. If noninterspersed-parity mode is selected, D8, D17, and D26 are assumed to be valid bits and D32, D33, D34, and D35 are ignored. Interspersed parity mode is selected during master reset by the state of the IP input. Interspersed parity control has an effect only during parallel programming of the offset registers. It does not affect data written to and read from the FIFO.
***AS INSTRU
The SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, and SN74V3690 are fabricated using high-speed submicron CMOS technology, and are characterized for operation from 0°C to 70°C.
Teil # Beschreibung Aktie Preis
SN74V3690-6PEU
DISTI # 296-14945-ND		IC 32768X36 FIFO MEMORY 128LQFP
RoHS: Not compliant
Min Qty: 1
Container: Tray		1454In Stock
  • 144:$31.0331
  • 72:$34.2435
  • 10:$35.7420
  • 1:$38.3100
SN74V3690-6PEU
DISTI # SN74V3690-6PEU		FIFO Mem Sync Dual Depth/Width Uni-Dir 32K x 36 128-Pin LQFP Tray - Trays (Alt: SN74V3690-6PEU)
RoHS: Not Compliant
Min Qty: 1
Container: Tray		Americas - 0
  • 1:$35.7900
  • 10:$34.8900
  • 25:$33.9900
  • 50:$33.0900
  • 100:$31.7900
  • 500:$31.0900
  • 1000:$30.4900
SN74V3690-6PEU
DISTI # SN74V3690-6PEU		FIFO Mem Sync Dual Depth/Width Uni-Dir 32K x 36 128-Pin LQFP Tray (Alt: SN74V3690-6PEU)
RoHS: Not Compliant
Min Qty: 1
Container: Tray		Europe - 0
  • 1:€32.3900
  • 10:€30.7900
  • 25:€29.2900
  • 50:€27.8900
  • 100:€26.6900
  • 500:€25.5900
  • 1000:€24.4900
SN74V3690-6PEU
DISTI # 595-SN74V3690-6PEU		FIFO 32768 x 36 Synch FIFO Memory
RoHS: Not compliant		89
  • 1:$36.4800
  • 5:$35.6700
  • 10:$34.0400
  • 25:$32.6200
  • 100:$29.5600
  • 250:$28.5400
SN74V3690-6PEUFIFO, 32KX36, 4.5ns, Synchronous, CMOS, PQFP128
RoHS: Not Compliant		371
  • 1000:$29.9900
  • 500:$31.5600
  • 100:$32.8600
  • 25:$34.2700
  • 1:$36.9100
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Verfügbarkeit
Aktie:
93
Auf Bestellung:
2076
Menge eingeben:
Der aktuelle Preis von SN74V3690-6PEU dient nur als Referenz. Wenn Sie den besten Preis erhalten möchten, senden Sie bitte eine Anfrage oder senden Sie eine direkte E-Mail an unser Verkaufsteam [email protected]
Referenzpreis (USD)
Menge
Stückpreis
ext. Preis
1
36,48 $
36,48 $
5
35,67 $
178,35 $
10
34,04 $
340,40 $
25
32,62 $
815,50 $
100
29,56 $
2 956,00 $
250
28,54 $
7 135,00 $
Aufgrund von Halbleiterknappheit ab 2021 ist der untere Preis der Normalpreis vor 2021. Bitte senden Sie eine Anfrage zur Bestätigung.
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