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MC100LVEL30DWR2

MC100LVEL30DWR2
Mfr. #:
MC100LVEL30DWR2
Hersteller:
Rochester Electronics, LLC
Beschreibung:
Flip Flops 3.3V/5V ECL Triple
Lebenszyklus:
Neu von diesem Hersteller.
Datenblatt:
MC100LVEL30DWR2 Datenblatt
Die Zustellung:
DHL FedEx Ups TNT EMS
Zahlung:
T/T Paypal Visa MoneyGram Western Union
ECAD Model:
Produkteigenschaft
Attributwert
Tags
MC100LVEL30DWR, MC100LVEL30, MC100LVEL3, MC100LVEL, MC100L, MC100, MC10, MC1
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We guarantee 100% customer satisfaction.

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We provide 90-360 days warranty.

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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***swan
IC FLIP FLOP TRPL D 3.3V 20-SOIC
***et
BBG ECL FLIP FLOP TRPL
***et
Flip Flop D-Primary-Secondary Type Pos-Edge 3-Element 20-Pin SOIC W T/R
***ponent Stockers USA
100EL SERIES POSITIVE EDGE TRIGGERED D FLIP-FLOP COMPLEMENTARY OUTPUT PDSO20
***emi
ECL Triple D Flip-Flop with Set and Reset
***et
Flip Flop D-Primary-Secondary Type Pos-Edge 3-Element 20-Pin SOIC W Rail
***ark
Flip Flop Logic IC; Logic Type:D-Type Flip-Flop; Logic Family:ECL; Logic Base Number:EL30; Frequency Max:1200MHz; Supply Voltage Min:4.2V; Supply Voltage Max:5V; Termination Type:SMD; Package/Case:20-SOIC; No. of Pins:20 ;RoHS Compliant: Yes
***th Star Micro
The MC100EL30 is a triple master-slave D flip flop with differential outputs. Data enters the master latch when the clock input is LOW and transfers to the slave upon a positive transition on the clock input. In addition to a common Set input individual Reset inputs are provided for each flip flop. Both the Set and Reset inputs function asynchronous and overriding with respect to the clock inputs.
***NGYU ELECTRONICS
IC FLIP FLOP ECL TRP DIFF 20SOIC
***roFlash
Bbg Ecl Flip Flop Trpl
***p One Stop Global
Flip Flop D-Type Bus Interface Pos-Edge 3-ST 1-Element 20-Pin SOIC Tube
***ment14 APAC
LOGIC, 3.3V OCT FLIP-FLOP, 20SOIC; Flip-Flop Type:D; Propagation Delay:3ns; Frequency:150MHz; Output Current:64mA; Trigger Type:Positive Edge; IC Output Type:Tri State Non Inverted; Supply Voltage Range:2.7V to 3.6V; Logic Case Style:SOIC; No. of Pins:20; Operating Temperature Range:-40°C to +85°C; SVHC:No SVHC (20-Jun-2011); Logic IC Base Number:74574; Logic IC Family:LVTH; Logic IC Function:Octal Edge Triggered D-Type Flip-Flop with 3-State Outputs; Output Type:Tri State Non Inverted; Package / Case:SOIC; Supply Voltage Max:3.6V; Supply Voltage Min:2.7V; Termination Type:SMD
***as Instruments
These octal flip-flops are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. The eight flip-flops of the ’LVTH574 devices are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. A buffered output-enable (OE\) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE\ does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.
***as Instruments
3.3-V ABT Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-SOIC -40 to 85
***ical
Flip Flop D-Type Bus Interface Pos-Edge 3-ST 1-Element 20-Pin SOIC Tube
***ment14 APAC
LOGIC, OCTAL F-F TRI-STATE, 20SOIC; Flip-Flop Type:D; Propagation Delay:2.9ns; Frequency:150MHz; Output Current:64mA; Trigger Type:Positive Edge; IC Output Type:Tri State Non Inverted; Supply Voltage Range:2.7V to 3.6V; Logic Case Style:SOIC; No. of Pins:20; Operating Temperature Range:-40°C to +85°C; SVHC:No SVHC (20-Jun-2011); Logic IC Base Number:74374; Logic IC Family:LVTH; Logic IC Function:Octal Edge-Triggered D-Type Flip-Flop with 3-State Outputs; Output Type:Tri State Non Inverted; Package / Case:SOIC; Supply Voltage Max:3.6V; Supply Voltage Min:2.7V; Termination Type:SMD
***as Instruments
3.3-V ABT Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-SOIC -40 to 85
***ical
Flip Flop D-Type Bus Interface Pos-Edge 3-ST 1-Element 20-Pin SOIC T/R
***ark
Flip-Flop Logic IC; Logic Family:LVT; Supply Voltage Min:2.7V; Supply Voltage Max:3.6V; Package/Case:20-SOIC; No. of Pins:20; Operating Temperature Range:-40°C to +85°C; Input Type:TTL/CMOS; Leaded Process Compatible:Yes ;RoHS Compliant: Yes
Teil # Mfg. Beschreibung Aktie Preis
MC100LVEL30DWR2G
DISTI # V36:1790_07316942		ON SemiconductorFlip Flop D-Master-Slave Type Pos-Edge 3-Element 20-Pin SOIC W T/R
RoHS: Compliant		0
  • 1000000:$6.4010
  • 500000:$6.4040
  • 100000:$6.6100
  • 10000:$6.9660
  • 1000:$7.0250
MC100LVEL30DWR2G
DISTI # MC100LVEL30DWR2G-ND		ON SemiconductorIC FF D-TYPE TRPL 1BIT 20SOIC
RoHS: Compliant
Min Qty: 1000
Container: Tape & Reel (TR)		Temporarily Out of Stock
  • 1000:$7.0245
MC100LVEL30DWR2G
DISTI # MC100LVEL30DWR2G		ON SemiconductorFlip Flop D-Master-Slave Type Pos-Edge 3-Element 20-Pin SOIC W T/R - Tape and Reel (Alt: MC100LVEL30DWR2G)
RoHS: Compliant
Min Qty: 1000
Container: Reel		Americas - 0
  • 10000:$6.4900
  • 6000:$6.5900
  • 4000:$6.6900
  • 2000:$6.7900
  • 1000:$6.8900
MC100LVEL30DWR2G
DISTI # MC100LVEL30DWR2G		ON SemiconductorFlip Flop D-Master-Slave Type Pos-Edge 3-Element 20-Pin SOIC W T/R (Alt: MC100LVEL30DWR2G)
RoHS: Compliant
Min Qty: 1000
Container: Tape and Reel		Asia - 0
  • 50000:$8.6584
  • 25000:$8.8027
  • 10000:$9.1062
  • 5000:$9.4314
  • 3000:$9.7807
  • 2000:$10.1569
  • 1000:$10.5632
MC100LVEL30DWR2G
DISTI # MC100LVEL30DWR2G		ON SemiconductorFlip Flop D-Master-Slave Type Pos-Edge 3-Element 20-Pin SOIC W T/R (Alt: MC100LVEL30DWR2G)
RoHS: Compliant
Min Qty: 1000
Container: Tape and Reel		Europe - 0
  • 10000:€6.1900
  • 6000:€6.5900
  • 4000:€7.1900
  • 2000:€7.3900
  • 1000:€7.7900
MC100LVEL30DWR2G
DISTI # 863-MC100LVEL30DWR2G		ON SemiconductorFlip Flops 3.3V/5V ECL Triple D-Type
RoHS: Compliant		666
  • 1:$11.0900
  • 10:$10.2000
  • 25:$9.7800
  • 100:$8.6100
  • 250:$8.1900
  • 500:$7.6600
  • 1000:$7.0300
MC100LVEL30DWR2
DISTI # 863-MC100LVEL30DWR2		ON SemiconductorFlip Flops 3.3V/5V ECL Triple
RoHS: Not compliant		0
    MC100LVEL30DWR2ON SemiconductorD Flip-Flop, 100LVEL Series, 1-Func, Positive Edge Triggered, 3-Bit, Complementary Output, ECL, PDSO20
    RoHS: Not Compliant    		310
    • 1000:$7.7900
    • 500:$8.2000
    • 100:$8.5400
    • 25:$8.9000
    • 1:$9.5900
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      Verfügbarkeit
      Aktie:
      Available
      Auf Bestellung:
      1000
      Menge eingeben:
      Der aktuelle Preis von MC100LVEL30DWR2 dient nur als Referenz. Wenn Sie den besten Preis erhalten möchten, senden Sie bitte eine Anfrage oder senden Sie eine direkte E-Mail an unser Verkaufsteam [email protected]
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      Aufgrund von Halbleiterknappheit ab 2021 ist der untere Preis der Normalpreis vor 2021. Bitte senden Sie eine Anfrage zur Bestätigung.
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