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SN74SSQEB32882ZALR

SN74SSQEB32882ZALR
Mfr. #:
SN74SSQEB32882ZALR
Beschreibung:
Registers 28-56 Bit Registered Buffer
Lebenszyklus:
Neu von diesem Hersteller.
Datenblatt:
SN74SSQEB32882ZALR Datenblatt
Die Zustellung:
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ECAD Model:
Mehr Informationen:
SN74SSQEB32882ZALR Mehr Informationen SN74SSQEB32882ZALR Product Details
Produkteigenschaft
Attributwert
Hersteller:
Texas Instruments
Produktkategorie:
Register
RoHS:
Y
Minimale Betriebstemperatur:
0 C
Maximale Betriebstemperatur:
+ 85 C
Paket / Koffer:
nFBGA-176
Verpackung:
Spule
Serie:
SN74SSQEB32882
Marke:
Texas Instruments
Feuchtigkeitsempfindlich:
ja
Produktart:
Register
Werkspackungsmenge:
2000
Unterkategorie:
Logik-ICs
Gewichtseinheit:
0.010935 oz
Tags
SN74SSQ, SN74SS, SN74S, SN74, SN7
Service Guarantees

We guarantee 100% customer satisfaction.

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We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
*** Stop Electro
PLL Based Clock Driver, S Series, 0 True Output(s), 0 Inverted Output(s), PBGA176
***ical
Registered Buffer Single-Element 28-CH 176-Pin NFBGA T/R
***as Instruments
945-MHz, JEDEC SSTE32882 compliant 28-bit to 56-bit registered buffer with address-parity test 176-NFBGA 0 to 85
***i-Key
IC REGSTR BUFFER 28-56BIT 176BGA
***et
Registering Clock Driver 176-Pin NFBGA T/R
***AS INST
This JEDEC SSTE32882 28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 registering clock driver with parity is designed for operation on DDR3 registered DIMMs with VDD of 1.5 V, on DDR3L registered DIMMs with VDD of 1.35 V and on DDR3U registered DIMMs with VDD of 1.25 V.
***AS INSTUMENTS
All inputs are 1.5 V, 1.35V and 1.25 V CMOS compatible. All outputs are CMOS drivers optimized to drive DRAM signals on terminated traces in DDR3 RDIMM applications. The clock outputs Yn and Yn and control net outputs DxCKEn, DxCSn and DxODTn can be driven with a different strength and skew to optimize signal integrity, compensate for different loading and equalize signal travel speed.
***OMO Electronic
The SN74SSQEB32882 has two basic modes of operation associated with the Quad Chip Select Enable (QCSEN) input. When the QCSEN input pin is open (or pulled high), the component has two chip select inputs, DCS0 and DCS1, and two copies of each chip select output, QACS0, QACS1, QBCS0 and QBCS1. This is the “QuadCS disabled” mode. When the QCSEN input pin is pulled low, the component has four chip select inputs DCS[3:0], and four chip select outputs, QCS[3:0]. This is the “QuadCS enabled” mode. Through the remainder of this specification, DCS[n:0] will indicate all of the chip select inputs, where n=1 for QuadCS disabled, and n=3 for QuadCS enabled. QxCS[n:0] will indicate all of the chip select outputs.
***AS INSTRUMENT
The device also supports a mode where a single device can be mounted on the back side of a DIMM. If MIRROR=HIGH, Input Bus Termination (IBT) has to stay enabled for all input signals in this case.
***AS USD
The SN74SSQEB32882 operates from a differential clock (CK and CK). Data are registered at the crossing of CK going HIGH, and CK going LOW. This data could be either re-driven to the outputs or it could be used to access device internal control registers.
***AS INTRUMENTS
The input bus data integrity is protected by a parity function. All address and command input signals are added up and the last bit of the sum is compared to the parity signal delivered by the system at the input PAR_IN one clock cycle later. If they do not match the device pulls the open drain output ERROUT LOW. The control signals (DCKE0, DCKE1, DODT0, DODT1, DCS[n:0]) are not part of this computation.
***
The SN74SSQEB32882 implements different power saving mechanisms to reduce thermal power dissipation and to support system power down states. By disabling unused outputs the power consumption is further reduced.
***NS
The package is optimized to support high density DIMMs. By aligning input and output positions towards DIMM finger signal ordering and SDRAM ballout the device de-scrambles the DIMM traces allowing low cross talk design with low interconnect latency.
***AS INSTRUMENTS INCORPORATED
Edge controlled outputs reduce ringing and improve signal eye opening at the SDRAM inputs.
Teil # Beschreibung Aktie Preis
SN74SSQEB32882ZALR
DISTI # 296-27685-1-ND		IC REGSTR BUFFER 28-56BIT 176BGA
RoHS: Compliant
Min Qty: 1
Container: Cut Tape (CT)		2205In Stock
  • 1000:$4.7722
  • 500:$5.4792
  • 100:$6.2922
  • 10:$7.6000
  • 1:$8.4100
SN74SSQEB32882ZALR
DISTI # 296-27685-6-ND		IC REGSTR BUFFER 28-56BIT 176BGA
RoHS: Compliant
Min Qty: 1
Container: Digi-Reel®		2205In Stock
  • 1000:$4.7722
  • 500:$5.4792
  • 100:$6.2922
  • 10:$7.6000
  • 1:$8.4100
SN74SSQEB32882ZALR
DISTI # 296-27685-2-ND		IC REGSTR BUFFER 28-56BIT 176BGA
RoHS: Compliant
Min Qty: 2000
Container: Tape & Reel (TR)		Temporarily Out of Stock
  • 2000:$4.4616
SN74SSQEB32882ZALR
DISTI # SN74SSQEB32882ZALR		Registering Clock Driver 176-Pin NFBGA T/R - Tape and Reel (Alt: SN74SSQEB32882ZALR)
RoHS: Compliant
Min Qty: 2000
Container: Reel		Americas - 0
  • 2000:$4.2900
  • 4000:$4.2900
  • 8000:$4.2900
  • 12000:$4.2900
  • 20000:$4.1900
SN74SSQEB32882ZALR
DISTI # SN74SSQEB32882ZALR		Registering Clock Driver 176-Pin NFBGA T/R (Alt: SN74SSQEB32882ZALR)
RoHS: Compliant
Min Qty: 2000
Container: Tape and Reel		Europe - 0
  • 2000:€5.6900
  • 4000:€4.9900
  • 8000:€4.4900
  • 12000:€4.2900
  • 20000:€4.0900
SN74SSQEB32882ZALRJEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test6000
  • 1000:$3.9000
  • 750:$3.9800
  • 500:$4.6000
  • 250:$5.2900
  • 100:$5.6600
  • 25:$6.3200
  • 10:$6.7600
  • 1:$7.5200
SN74SSQEB32882ZALR
DISTI # 595-74SSQEB32882ZALR		Registers 28-56 Bit Registered Buffer
RoHS: Compliant		0
  • 1:$8.1700
  • 10:$7.3800
  • 25:$6.8300
  • 100:$6.1100
  • 250:$5.8000
  • 500:$5.3200
  • 1000:$4.6400
  • 2000:$4.4700
Bild Teil # Beschreibung
SN74SSQEB32882ZALR

Mfr.#: SN74SSQEB32882ZALR

OMO.#: OMO-SN74SSQEB32882ZALR

 Registers 28-56 Bit Registered Buffer
SN74SSQEB32882ZALR

Mfr.#: SN74SSQEB32882ZALR

OMO.#: OMO-SN74SSQEB32882ZALR-TEXAS-INSTRUMENTS

 Registers 28-56 Bit Registered Buffe
Verfügbarkeit
Aktie:
Available
Auf Bestellung:
1985
Menge eingeben:
Der aktuelle Preis von SN74SSQEB32882ZALR dient nur als Referenz. Wenn Sie den besten Preis erhalten möchten, senden Sie bitte eine Anfrage oder senden Sie eine direkte E-Mail an unser Verkaufsteam [email protected]
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