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SN74LV166APWTG4

SN74LV166APWTG4
Mfr. #:
SN74LV166APWTG4
Beschreibung:
Counter Shift Registers Parallel Load 8B Shift Registers
Lebenszyklus:
Neu von diesem Hersteller.
Datenblatt:
SN74LV166APWTG4 Datenblatt
Die Zustellung:
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ECAD Model:
Mehr Informationen:
SN74LV166APWTG4 Mehr Informationen SN74LV166APWTG4 Product Details
Produkteigenschaft
Attributwert
Hersteller:
Texas Instruments
Produktkategorie:
Zählerschieberegister
RoHS:
Y
Zählreihenfolge:
Seriell/Parallel zu Seriell
Anzahl Kreise:
1
Anzahl der Bits:
8 bit
Paket / Koffer:
TSSOP-16
Logikfamilie:
LV
Logiktyp:
CMOS
Anzahl der Eingabezeilen:
9
Ausbreitungsverzögerungszeit:
23.3 ns, 18.9 ns, 11.9 ns
Versorgungsspannung - Max.:
5.5 V
Minimale Betriebstemperatur:
- 40 C
Maximale Betriebstemperatur:
+ 85 C
Verpackung:
Spule
Funktion:
Schieberegister
Breite:
4.4 mm
Marke:
Texas Instruments
Montageart:
SMD/SMT
Anzahl der Ausgangsleitungen:
1
Betriebsversorgungsspannung:
2.5 V, 3.3 V, 5 V
Produktart:
Zählerschieberegister
Werkspackungsmenge:
1
Unterkategorie:
Logik-ICs
Gewichtseinheit:
0.002169 oz
Tags
SN74LV166AP, SN74LV166, SN74LV16, SN74LV1, SN74LV, SN74L, SN74, SN7
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Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
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Email: [email protected]

Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***i-Key
IC SHIFT REGISTER SGL 8B 16TSSOP
***ark
Register Logic IC; Logic Family:LV-A; Supply Voltage Min:2V; Supply Voltage Max:5.5V; Package/Case:16-TSSOP; No. of Pins:16; Operating Temperature Range:-40°C to +85°C; Input Type:LVTTL; Leaded Process Compatible:Yes ;RoHS Compliant: Yes
***as Instruments
The 'LV166A devices are 8-bit parallel-load shift registers, designed for 2-V to 5.5-V VCC operation. The 'LV166A parallel-in or serial-in, serial-out registers feature gated clock (CLK, CLK INH) inputs and an overriding clear (CLR\) input. The parallel-in or serial-in modes are established by the shift/load (SH/LD\) input. When high, SH/LD\ enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each clock (CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the low-to-high-level edge of CLK through a 2-input positive-NOR gate, permitting one input to be used as a clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either low enables the other clock input. This allows the system clock to be free running, and the register can be stopped on command with the other clock input. CLK INH should be changed to the high level only when CLK is high. CLR\ overrides all other inputs, including CLK, and resets all flip-flops to zero. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
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 Neu und Original
Verfügbarkeit
Aktie:
Available
Auf Bestellung:
1500
Menge eingeben:
Der aktuelle Preis von SN74LV166APWTG4 dient nur als Referenz. Wenn Sie den besten Preis erhalten möchten, senden Sie bitte eine Anfrage oder senden Sie eine direkte E-Mail an unser Verkaufsteam [email protected]
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