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SN74V283-15PZA

SN74V283-15PZA
Mfr. #:
SN74V283-15PZA
Beschreibung:
FIFO 32768 x 18 Synch FIFO Memory
Lebenszyklus:
Neu von diesem Hersteller.
Datenblatt:
SN74V283-15PZA Datenblatt
Die Zustellung:
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Mehr Informationen:
SN74V283-15PZA Mehr Informationen SN74V283-15PZA Product Details
Produkteigenschaft
Attributwert
Hersteller:
Texas Instruments
Produktkategorie:
FIFO
RoHS:
Y
Datenbusbreite:
9 bit, 18 bit
Busrichtung:
Unidirektional
Speichergröße:
576 kbit
Timing-Typ:
Synchron
Organisation:
64 k x 9, 32 k x 18
Anzahl Kreise:
2
Maximale Taktfrequenz:
66.7 MHz
Zugriffszeit:
10 ns
Versorgungsspannung - Max.:
3.45 V
Versorgungsspannung - Min.:
3.15 V
Versorgungsstrom - Max.:
35 mA
Minimale Betriebstemperatur:
0 C
Maximale Betriebstemperatur:
+ 70 C
Paket / Koffer:
LQFP-80
Verpackung:
Tablett
Höhe:
1.4 mm
Serie:
SN74V283
Breite:
14 mm
Marke:
Texas Instruments
Montageart:
SMD/SMT
Feuchtigkeitsempfindlich:
ja
Betriebsversorgungsspannung:
3.3 V
Produktart:
FIFO
Werkspackungsmenge:
90
Unterkategorie:
Speicher & Datenspeicherung
Gewichtseinheit:
0.022575 oz
Tags
SN74V283-1, SN74V28, SN74V2, SN74V, SN74, SN7
Service Guarantees

We guarantee 100% customer satisfaction.

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We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
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we buy and manage excess electronic components, including excess inventory identified for disposal.
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
    S***s
    S***s
    BR

    Came 3 requests in a single free. Was to be cheaper.

    2019-06-21
    V***k
    V***k
    RU

    In a puffy bag it came perfectly. Looks like the original. Time will show.

    2019-03-31
***ical
FIFO Mem Sync Dual Depth/Width Uni-Dir 32K x 18/64K x 9 80-Pin LQFP Tray
***as Instruments
32768 x 18 Synchronous FIFO Memory 80-LQFP 0 to 70
***ark
FIFO Logic IC; Frequency Max:166MHz; Supply Voltage Min:3.15V; Supply Voltage Max:3.45V; Package/Case:80-LQFP; No. of Pins:80; Operating Temperature Range:0°C to +70°C; Peak Reflow Compatible (260 C):No ;RoHS Compliant: Yes
***AS INSTRUMENTS INC
The SN74V263, SN74V273, SN74V283, and SN74V293 are exceptionally deep, high-speed, CMOS first-in first-out (FIFO) memories with clocked read and write controls and a flexible bus-matching ×9/×18 data flow.
***OMO Electronic
There is flexible ×9/×18 bus matching on both read and write ports.
***AS INS
The period required by the retransmit operation is fixed and short.
***AS INSTR
The first-word data-latency period, from the time the first word is written to an empty FIFO to the time it can be read, is fixed and short.
***AS INSTRUMENT
These FIFOs are particularly appropriate for network, video, telecommunications, data communications, and other applications that need to buffer large amounts of data and match buses of unequal sizes.
***AS
Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume either an 18-bit or 9-bit width, as determined by the state of external control pins’ input width (IW) and output width (OW) during the master-reset cycle.
***AS INST
The input port is controlled by write-clock (WCLK) and write-enable (WEN)\ inputs. Data is written into the FIFO on every rising edge of WCLK when WEN\ is asserted. The output port is controlled by read-clock (RCLK) and read-enable (REN)\ inputs. Data is read from the FIFO on every rising edge of RCLK when REN\ is asserted. An output-enable (OE)\ input is provided for 3-state control of the outputs.
***AS INSRUMENTS
The frequencies of both the RCLK and the WCLK signals can vary from 0 to fMAX, with complete independence. There are no restrictions on the frequency of one clock input with respect to the other.
***AS INSTRUMEN
There are two possible timing modes of operation with these devices: first-word fall-through (FWFT) mode and standard mode.
***AS
In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. REN\ need not be asserted for accessing the first word. However, subsequent words written to the FIFO do require a low on REN\ for access. The state of the FWFT/SI input during master reset determines the timing mode in use.
***AS INSTUMENTS
In standard mode, the first word written to an empty FIFO does not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating REN\ and enabling a rising RCLK edge, shifts the word from internal memory to the data output lines.
***OMO Electronic
For applications requiring more data-storage capacity than a single FIFO can provide, the FWFT timing mode permits depth expansion by chaining FIFOs in series (i.e., the data outputs of one FIFO are connected to the corresponding data inputs of the next). No external logic is required.
***
These FIFOs have five flag pins: empty flag or output ready (EF\/OR\), full flag or input ready (FF\/IR\), half-full flag (HF)\, programmable almost-empty flag (PAE)\, and programmable almost-full flag (PAF)\. The IR\ and OR\ functions are selected in FWFT mode. The EF\ and FF\ functions are selected in standard mode. HF\, PAE\, and PAF\ always are available for use, regardless of timing mode.
***AS USD
PAE\ and PAF\ can be programmed independently to switch at any point in memory. Programmable offsets determine the flag-switching threshold and can be loaded by parallel or serial methods. Eight default offset settings also are provided, so that PAE\ can be set to switch at a predefined number of locations from the empty boundary. The PAF\ threshold also can be set at similar predefined values from the full boundary. The default offset values are set during master reset by the state of FSEL0, FSEL1, and LD\.
***AS
For serial programming, SEN\, together with LD\, loads the offset registers via the serial input (SI) on each rising edge of WCLK. For parallel programming, WEN\, together with LD\, loads the offset registers via Dn on each rising edge of WCLK. REN\, together with LD\, can read the offsets in parallel from Qn on each rising edge of RCLK, regardless of whether serial or parallel offset loading has been selected.
***ASI
Also, the timing modes of PAE\ and PAF\ outputs can be selected. Timing modes can be set to be either asynchronous or synchronous for PAE\ and PAF\.
***as Instruments Inc.
If the asynchronous PAE\/PAF\ configuration is selected, PAE\ is asserted low on the low-to-high transition of RCLK. PAE\ is reset to high on the low-to-high transition of WCLK. Similarly, PAF\ is asserted low on the low-to-high transition of WCLK, and PAF\ is reset to high on the low-to-high transition of RCLK.
***NS
If the synchronous PAE\/PAF\ configuration is selected , PAE\ is asserted and updated on the rising edge of RCLK only and not WCLK. Similarly, PAF\ is asserted and updated on the rising edge of WCLK only and not RCLK. The desired mode is configured during master reset by the state of the programmable-flag mode (PFM) pin.
***XS
The retransmit function allows data to be reread from the FIFO more than once. A low on the RT\ input during a rising RCLK edge initiates a retransmit operation by setting the read pointer to the first location of the memory array. Zero-latency retransmit timing mode can be selected using the retransmit timing mode (RM). During master reset, a low on RM selects zero-latency retransmit. A high on RM during master reset selects normal latency.
***TEXAS
If zero-latency retransmit operation is selected, the first data word to be retransmitted is placed on the output register with respect to the same RCLK edge that initiated the retransmit, if RT\ is low.
***AS INSTRUMENTS INC
During master reset (MRS)\, the functions for all the operating modes are programmed. These include FWFT or standard timing, input bus width, output bus width, big endian or little endian, retransmit mode, programmable-flag operating and programming method, programmable-flag default offsets, and interspersed parity select. The read and write pointers are set to the first location of the FIFO. Then, based on the selected timing mode, EF\ is set low or OR\ is set high and FF\ is set high or IR\ is set low. Also, PAE\ is set low, PAF\ is set high, and HF\ is set high. The Q outputs are set low.
***OMO Electronic
Partial reset (PRS)\ also sets the read and write pointers to the first location of the memory. However, the timing mode, programmable-flag programming method, default or programmed offset settings, input and output bus widths, big endian/little endian, interspersed parity select, and retransmit mode existing before partial reset is asserted remain unchanged. The flags are updated according to the timing mode and offsets in effect. PRS\ is useful for resetting a device in mid-operation when reprogramming programmable flags and other functions would be undesirable.
***AS
A big-endian/little-endian data word format is provided. This function is useful when data is written into the FIFO in long-word (×18) format and read out of the FIFO in small-word (×9) format. If big-endian mode is selected, the most significant byte (MSB) (word) of the long word written into the FIFO is read out of the FIFO first, followed by the least significant byte (LSB). If little-endian format is selected, the LSB of the long word written into the FIFO is read out first, followed by the MSB. The mode desired is configured during master reset by the state of the big-endian/little-endian (BE)\ pin.
***XS
The interspersed/noninterspersed parity (IP) bit function allows the user to select the parity bit in the word loaded into the parallel port (D0–Dn) when programming the flag offsets. If interspersed-parity mode is selected, the FIFO assumes that the parity bit is located in bit position D8 during the parallel programming of the flag offsets. If noninterspersed-parity mode is selected, D8 is assumed to be a valid bit and D16 and D17 are ignored. IP mode is selected during master reset by the state of the IP input pin. This mode is relevant only when the input width is set to ×18 mode.
***INS
The SN74V263, SN74V273, SN74V283, and SN74V293 are fabricated using TI’s high-speed submicron CMOS technology.
***ASI
For more information on this device family, see the following application reports:
Teil # Beschreibung Aktie Preis
SN74V283-15PZA
DISTI # 26627199		FIFO Mem Sync Dual Depth/Width Uni-Dir 32K x 18/64K x 9 80-Pin LQFP Tray
RoHS: Compliant		1350
  • 450:$42.6514
SN74V283-15PZA
DISTI # 296-12486-ND		IC SYNC FIFO MEM 32768X18 80LQFP
RoHS: Compliant
Min Qty: 90
Container: Tray		Temporarily Out of Stock
  • 90:$50.1581
SN74V283-15PZA
DISTI # V39:1801_07360556		FIFO Mem Sync Dual Depth/Width Uni-Dir 32K x 18/64K x 9 80-Pin LQFP Tray
RoHS: Compliant		0
    SN74V283-15PZA
    DISTI # SN74V283-15PZA    		FIFO Mem Sync Dual Depth/Width Uni-Dir 32K x 18/64K x 9 80-Pin LQFP - Trays (Alt: SN74V283-15PZA)
    RoHS: Not Compliant
    Min Qty: 90
    Container: Tray    		Americas - 0
      SN74V283-15PZA
      DISTI # SN74V283-15PZA      		FIFO Mem Sync Dual Depth/Width Uni-Dir 32K x 18/64K x 9 80-Pin LQFP (Alt: SN74V283-15PZA)
      RoHS: Compliant
      Min Qty: 90      		Europe - 0
      • 900:€36.2900
      • 540:€37.1900
      • 360:€38.2900
      • 180:€40.4900
      • 90:€42.9900
      SN74V283-15PZA
      DISTI # 595-SN74V283-15PZA      		FIFO 32768 x 18 Synch FIFO Memory
      RoHS: Compliant      		0
      • 90:$47.7700
      • 180:$43.3000
      SN74V283-15PZAFIFO, 32KX18, 10ns, Synchronous, CMOS, PQFP80
      RoHS: Compliant      		1266
      • 1000:$39.2900
      • 500:$41.3600
      • 100:$43.0600
      • 25:$44.9000
      • 1:$48.3600
      Bild Teil # Beschreibung
      SN74V283PZAEP

      Mfr.#: SN74V283PZAEP

      OMO.#: OMO-SN74V283PZAEP

      		 FIFO Mil Enhance 32768x18 Synch FIFO Memory
      SN74V283-10PZA

      Mfr.#: SN74V283-10PZA

      OMO.#: OMO-SN74V283-10PZA

      		 FIFO 32768 x 18 Synch FIFO Memory
      SN74V283-6PZA

      Mfr.#: SN74V283-6PZA

      OMO.#: OMO-SN74V283-6PZA

      		 FIFO 32768 x 18 Synch FIFO Memory
      SN74V283-7GGM

      Mfr.#: SN74V283-7GGM

      OMO.#: OMO-SN74V283-7GGM

      		 FIFO 32768 x 18 Synch FIFO Memory
      SN74V283-15GGM

      Mfr.#: SN74V283-15GGM

      OMO.#: OMO-SN74V283-15GGM

      		 FIFO 32768 x 18 Synch FIFO Memory
      SN74V283-7PZA

      Mfr.#: SN74V283-7PZA

      OMO.#: OMO-SN74V283-7PZA

      		 FIFO 32768 x 18 Synch FIFO Memory
      SN74V283PZAEP

      Mfr.#: SN74V283PZAEP

      OMO.#: OMO-SN74V283PZAEP-TEXAS-INSTRUMENTS

      		 FIFO Mil Enhance 32768x18 Synch FIFO Memory
      SN74V283-15PZA

      Mfr.#: SN74V283-15PZA

      OMO.#: OMO-SN74V283-15PZA-TEXAS-INSTRUMENTS

      		 FIFO 32768 x 18 Synch FIFO Memory
      SN74V283-6PZA

      Mfr.#: SN74V283-6PZA

      OMO.#: OMO-SN74V283-6PZA-TEXAS-INSTRUMENTS

      		 FIFO 32768 x 18 Synch FIFO Memory
      SN74V283-7PZA

      Mfr.#: SN74V283-7PZA

      OMO.#: OMO-SN74V283-7PZA-TEXAS-INSTRUMENTS

      		 FIFO 32768 x 18 Synch FIFO Memory
      Verfügbarkeit
      Aktie:
      Available
      Auf Bestellung:
      1000
      Menge eingeben:
      Der aktuelle Preis von SN74V283-15PZA dient nur als Referenz. Wenn Sie den besten Preis erhalten möchten, senden Sie bitte eine Anfrage oder senden Sie eine direkte E-Mail an unser Verkaufsteam [email protected]
      Referenzpreis (USD)
      Menge
      Stückpreis
      ext. Preis
      90
      47,77 $
      4 299,30 $
      180
      43,30 $
      7 794,00 $
      270
      41,80 $
      11 286,00 $
      Aufgrund von Halbleiterknappheit ab 2021 ist der untere Preis der Normalpreis vor 2021. Bitte senden Sie eine Anfrage zur Bestätigung.
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