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SN74GTLP21395PWE4

SN74GTLP21395PWE4
Mfr. #:
SN74GTLP21395PWE4
Beschreibung:
Translation - Voltage Levels Quad Bus Buff Gate W/3-St Otpt
Lebenszyklus:
Neu von diesem Hersteller.
Datenblatt:
SN74GTLP21395PWE4 Datenblatt
Die Zustellung:
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Mehr Informationen:
SN74GTLP21395PWE4 Mehr Informationen SN74GTLP21395PWE4 Product Details
Produkteigenschaft
Attributwert
Hersteller:
Texas Instruments
Produktkategorie:
Übersetzung - Spannungsebenen
RoHS:
Y
Ausbreitungsverzögerungszeit:
10.4 ns
Versorgungsspannung - Max.:
3.45 V
Versorgungsspannung - Min.:
3.15 V
Minimale Betriebstemperatur:
- 40 C
Maximale Betriebstemperatur:
+ 85 C
Montageart:
SMD/SMT
Paket / Koffer:
TSSOP-20
Verpackung:
Rohr
Funktion:
Edge-Rate-Bus-Transceiver
Ausgabetyp:
3-State
Marke:
Texas Instruments
Logikfamilie:
74GT
Anzahl der Kanäle:
2 Channel
Ausgangsstrom auf hohem Niveau:
- 12 mA
Niedriger Ausgangsstrom:
100 mA
Produktart:
Übersetzung - Spannungsebenen
Werkspackungsmenge:
1
Unterkategorie:
Logik-ICs
Gewichtseinheit:
0.002751 oz
Tags
SN74GTLP21395P, SN74GTLP21, SN74GTLP2, SN74GTLP, SN74G, SN74, SN7
Service Guarantees

We guarantee 100% customer satisfaction.

Quality Guarantees

We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***i-Key
IC TXRX BUS ADJ EDGE DL 20-TSSOP
***as Instruments
The SN74GTLP21395 is two 1-bit, high-drive, 3-wire bus transceivers that provide LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation for applications, such as primary and secondary clocks, that require individual output-enable and true/complement controls. The device allows for transparent and inverted transparent modes of data transfer with separate LVTTL input and LVTTL output pins, which provide a feedback path for control and diagnostics monitoring. The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels and is designed especially to work with the Texas Instruments 3.3-V 1394 backplane physical-layer controller. High-speed (about three times faster than standard LVTTL or TTL) backplane operation is a direct result of GTLP reduced output swing (<1 V), reduced input threshold levels, improved differential input, OEC™ circuitry, and TI-OPC™ circuitry. Improved GTLP OEC and TI-OPC circuitry minimizes bus settling time, and have been designed and tested using several backplane models. The high drive allows incident-wave switching in heavily loaded backplanes, with equivalent load impedance down to 11 . The Y outputs, which are designed to sink up to 12 mA, include equivalent 26- resistors to reduce overshoot and undershoot. GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The ac specification of the SN74GTLP21395 is given only at the preferred higher noise margin GTLP, but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 V and VREF = 1 V) signal levels. For information on using GTLP devices in FB+/BTL applications, refer to TI application reports, Texas Instruments GTLP Frequently Asked Questions, literature number SCEA019, and GTLP in BTL Applications, literature number SCEA017. Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels, but are 5-V tolerant and are compatible with TTL or 5-V CMOS devices. VREF is the B-port differential input reference voltage. This device is fully specified for live-insertion applications using Ioff , power-up 3-state, and BIAS VCC . The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-insertion capability. This GTLP device features TI-OPC circuitry, which actively limits the overshoot caused by improperly terminated backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal integrity, which allows adequate noise margin to be maintained at higher frequencies. High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC input voltage between low and high adjusts the B-port output rise and fall times.This allows the designer to optimize system data-transfer rate and signal integrity to the backplane load. When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, the output-enable (OE\) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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Verfügbarkeit
Aktie:
Available
Auf Bestellung:
1500
Menge eingeben:
Der aktuelle Preis von SN74GTLP21395PWE4 dient nur als Referenz. Wenn Sie den besten Preis erhalten möchten, senden Sie bitte eine Anfrage oder senden Sie eine direkte E-Mail an unser Verkaufsteam [email protected]
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